Vanguard International Semiconductor Singapore – Intern, ETCH Process

Company
Vanguard International Semiconductor Singapore
vis-sgp.com
Designation
Intern, ETCH Process
Date Listed
16 Dec 2021
Job Type
Entry Level / Junior Executive
Intern/TS
Job Period
Immediate Start, For At Least 6 Months
Profession
Engineering
Industry
Electronics
Location Name
Tampines, Singapore
Address
Tampines, Singapore
Map
Allowance / Remuneration
$700 - 1,000 monthly
Company Profile

Vanguard International Semiconductor Corporation (VIS) is a leading specialty IC foundry service provider. Since its founding in December 1994 in Hsinchu Science Park, Taiwan, VIS has been achieving continuous success in its technology development and production efficiency improvement. VIS has also been consistently offering its customers cost-effective solutions and high value-added services. VIS currently has three 8-inch fabs with a monthly capacity of approximately 199,000 wafers in 2018. VIS headquarters is located at 123, Park Ave. 3, Hsinchu Science Park, Hsinchu, Taiwan.

In 2019, VIS acquired GLOBALFOUNDRIES’ Fab 3E 8-inch fab in Singapore. The transaction included buildings, facilities, equipment, and MEMS IPs and related business. After the one-year transfer period, VIS will take over full operation and management of the fab in 2020, which will become the fourth Fab of VIS, as well as the first overseas fab of VIS. VIS has reached maximum capacity in 2018, and its customers expect the company to expand to satisfy growing demands. This acquisition of asset is projected to increase the annual capacity of VIS by 400,000 8-inch wafers, demonstrating the determination and commitment of VIS to expand capacity.

We sincerely invite you to join VIS SG and to become a leader in semiconductor with us!

Job Description

Key Project: Process Equipment matching and FA analysis

1) Check tool to tool process parameter difference. Use SPC as tool to analyze and reporting

2) Perform Wafer Cross Section to determine the Etch Rate Profile. Upload data to server and charts for analysis

3) Reduce wafer scraps through day to day alarms analysis, focus on repeat alarms

Learning Outcomes:

1) Tool to tool matching for better process qualification

2) Speed up and Support Fab ramp for Etch module

3) Wafer scraps reduction, meeting line yield target

Requirements:

1) Diploma / University student, preferably in Engineering

2) Microsoft Office especially Excel

3) Keen sense of learning

4) Good personality

This position is already closed and no longer available.  You may like to view the other latest internships here.

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